In many electronic devices, signals are coupled through parallel signal lines that are positioned closely adjacent each other. For example, in a double in-line memory module (“DIMM”) 10 shown in FIG. 1, a plurality of memory devices, generally synchronous dynamic random access memory (“SDRAM”) devices 14, are mounted on an insulative substrate 16. Each of the SDRAM devices 14 has a set of external terminals that are coupled to respective contacts of edge an connector 18 through a set of buses 20 composed of a large number conductors running closely adjacent each other. Conductors of this type are commonly referred to a “microstrip” conductors, and they essentially function as transmission lines.
As is well known in the art, the transmission lines formed by the microstrip conductors in the buses 20 behave essentially as series inductors and resistors, and shunt capacitors. As shown in FIG. 2, signal S1 is generated by a signal source 36 having an output impedance represented by a resistor 38, and is coupled through a conductor 40. The conductor 40 is coupled to a termination voltage VTT through a termination impedance represented by a resistor 46. Another conductor 48 is represented by these same components, which have been provided with the same reference numerals. Intermediate sections 50 of the conductor 40, 48 are often parallel and closely adjacent each other. As explained in greater detail below, placing conductors adjacent to each other in this manner can create jitter in signals coupled through the conductors 40, 48.
Returning to FIG. 1, the conductors in the DIMM 10 couple command signals, address signals, write data signals, clock signals and often a write strobe signal to the SDRAM devices 14, and they couple read data signals and often a read strobe signal from the SDRAM devices 14. As the operating speeds of electronic devices, such as memory devices, continues to increase, the relative timing of digital signals has become even more critical. For example, in the DIMM 10 of FIG. 1, the write data signals are latched into the SDRAM devices 14 responsive to a write strobe signal. The write data signals are normally in phase with a system clock signal while the write strobe signal is the quadrature of the system clock signal. Transitions of the write strobe signal thus occur in the center of a data valid “eye” in which the write data signals are valid. As the operating speed of the SDRAM devices 14 continues to increase, the size of the data valid eye has become smaller, thus making the timing of the write strobe signal relative to the write data signals even more critical.
The timing of a digital signal is affected by “jitter,” which is high frequency phase noise that cause rapid changes in the timing at which transitions of the digital signal occur. Jitter can be caused by a number of sources, such as noise coupled to digital circuits along with a digit signal, which causes the switching time of the digital circuit to vary in a random manner. Jitter can also be caused by variations in the propagation time of digital signals coupled through signal lines. A pair of microstrip signal lines 70, 72 formed by a pair of conductive traces 74, 76 on a substrate 78 are shown in FIG. 3. The velocity at which signals propagate through the signal lines 70, 72 is proportional to the reciprocal of the square root of the dielectric constant of the signal lines 70, 72. Unfortunately, the dielectric constants of the signal lines 70, 72 vary because of the coupling of signal transitions in one line 70, 72 to the other line 70, 72. In particular, the effective dielectric constant of the signal lines 70, 72 will be different in each of the following cases:                When signals in adjacent signal lines 70, 72 transition in opposite directions (i.e., one line transitions high and the other line transitions low);        When signals in adjacent signal lines 70, 72 transition in the same direction; and        When a signal in one of the signal lines 70, 72 transitions and a signal the other line does not transition.        
As a result of these variations in the effective dielectric constants of the signal lines 70, 72, the time required for signals to propagate through the signal lines also varies. More specifically, the propagation velocity of the signals are highest when the signals transition in opposite directions. The propagation velocity is slower when one of the signals switches but the other does not. The propagation velocity is even slower when both of the signals switch in the same direction. Thus, for example, if the signal lines 70, 72 couples write data signals to one of the SDRAM devices 14 (FIG. 1), and a write data strobe is also coupled to the SDRAM devices 14, the relative timing of the write data signals relative to the write data strobe signal will vary depending on the relationship between the transitions of the write data signals. As a result, the transition of the write strobe signal may occur at the center of the data valid eye if the write data signals transition in the same direction, but it may miss the data valid eye if the write data signals transition in opposite directions. Under these circumstances, the correct write data will not be stored in the SDRAM device 14. Similar problems exist in coupling other signals to the SDRAM device 14 as well as coupling signals from the SDRAM device 14.
There is therefore a need for a system and method that can avoid the effects of jitter produced by coupling signals through signal lines that are closely adjacent each other.